By Himanshu Bhatnagar
The emphasis of this publication is on real-time program of Synopsys instruments, used to wrestle a number of difficulties noticeable at VDSM geometries. Readers may be uncovered to an efficient layout method for dealing with advanced, sub-micron ASIC designs. value is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to format, actual synthesis, and static timing research. At every one step, difficulties similar to every section of the layout stream are pointed out, with options and work-around defined intimately. moreover, an important concerns similar to format, together with clock tree synthesis and back-end integration (links to format) also are mentioned at size. in addition, the ebook comprises in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding types, special in the direction of optimum synthesis resolution.
objective audiences for this ebook are practising ASIC layout engineers and masters point scholars venture complicated VLSI classes on ASIC chip layout and DFT techniques.
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Additional info for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime®
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime® by Himanshu Bhatnagar